1. Field of the Invention
The present invention relates to the dicing of microelectronic device wafers into individual microelectronic dice. In particular, the present invention relates to forming trenches in the dicing streets of a microelectronic device wafer. These trenches assist in the prevention of defects, such as cracks and delamination, from forming and/or propagating in the interconnect layer of the integrated circuitry of the microelectronic device wafer.
2. State of the Art
In the production of microelectronic devices, integrated circuitry is formed in and on semiconductor wafers, which is usually comprised primarily of silicon, although other materials such as gallium arsenide and indium phosphide may be used. As shown in FIG. 15, a single microelectronic device wafer 200 may contain a plurality of substantially identical integrated circuits 202, which are usually substantially rectangular and arranged in rows and columns. Two sets of mutually parallel dicing streets 204 extend perpendicular to each other over substantially the entire surface of the semiconductor wafer 200 between each discrete integrated circuit 202.
After the integrated circuits 202 on the microelectronic device wafer 200 have been subjected to preliminary testing for functionality (wafer sort), the microelectronic device wafer 200 is diced (cut apart), so that each area of functioning integrated circuitry 202 becomes a microelectronic die that can be used to form a packaged microelectronic device. One exemplary microelectronic wafer dicing process uses a circular diamond-impregnated dicing saw, which travels down two mutually perpendicular sets of lines or “dicing streets” 204 lying between each of the rows and columns. Of course, the dicing streets 204 must be sized to allow passage of a wafer saw blade between adjacent integrated circuits 202 without causing damage to the circuitry.
As shown in FIGS. 16 and 17, a microelectronic device wafer 200 may have guard rings 206 which substantially surround the integrated circuit 202. The guard rings 206 extend though an interconnect layer 208 (see FIG. 17). The interconnect layer 208 comprises layers 212 consisting of metal traces layer separated by dielectric material layers on a semiconductor wafer 214. The interconnect layer 208 provides routes for electrical communication between integrated circuit components within the integrated circuits. The guard ring 206 is generally formed layer by layer as the interconnect layer 208 is formed. The guard ring 206 assists in preventing external contamination encroaching into the integrated circuitry 202 between the interconnect layer 208.
Prior to dicing, the microelectronic device wafer 200 is mounted onto a sticky, flexible tape 216 (shown in FIG. 17) that is attached to a ridge frame (not shown). The tape 216 continues to hold the microelectronic die after the dicing operation and during transport to the next assembly step. As shown in FIGS. 18 and 19, a saw cuts a channel 218 in the dicing street 204 through the interconnect layer 208 and the semiconductor wafer 214. During cutting, the saw generally cuts into the tape 216 to up to about one-third of its thickness.
However, in the dicing of microelectronic device wafers 200, the use of industry standard dicing saws (metal impregnated with diamond) results in a rough edge along the interconnect layer 208 and results in stresses being imposed on the interconnect layer 212. This effect is most prevalent with the interconnect layer 208 having ductile copper traces or interconnects. This rough edge and the stresses imposed is a source of crack propagation into and/or delamination of the interconnect layer 208, through the guard ring 206, and into the integrated circuitry 202 causing fatal defects. These defects are increasing as the device material properties move toward weaker adhesions and strengths in order to meet various electrical property requirements.
Therefore, it would be advantageous to develop techniques to effectively dice microelectronic device wafers while reducing or substantially eliminating the possibility of crack and delamination propagation.